In a radio communications system utilizing frequency multiplexing and time division multiplexing such as a cellular telephone system, one communication channel is assigned to one portable telephone, or terminal, so that the transmission and reception of data between the terminal and a base station are effected over this communication channel on a time division basis. Since such a radio communications system uses a large number of different frequencies, a phase-locked loop (PLL) synthesizer is used in each terminal as a carrier wave generator to make the terminal tune to an assigned channel, or frequency.
A frequency band assigned to communications channels is comparatively narrow in frequency. In order to efficiently generate a carrier wave having a desired frequency band and to perform fast frequency switching, a direct digital synthesizer (DDS) circuit is utilized to generate a reference frequency signal in the PLL synthesizer. Reference is made to U.S. Pat. No. 4,965,533 issued to R. P. Gilmore on Oct. 23, 1990.
The DDS circuit retrieves waveform data preliminarily stored in a ROM (read-only memory) in each sampling period corresponding to a specified output frequency, generates a digital signal which conforms an output signal of the given output frequency, and then transforms the digital signal into a desired analog signal to form a reference frequency signal. Hence, the reference frequency signal inherently involves a waveform distortion due to quantization errors, which distortion results in spurious signals and degradation in the carrier-to-noise (C/N) ratio of the output signal of a utilizing device such as a transmitter.
Further, since circuit elements such as a digital-to-analog (D/A) converter contained in the DDS circuit must have high speed operability, the synthesizer consumes undesirably great power.